The present invention generally relates to data coding for data storage systems and particularly relates to data encoding and decoding methods and apparatus for data storage systems.
There is an increasing demand at least in the field of magnetic recording and optical recording systems for inner codes that constrain channel input sequences so that they have certain desired properties for timing recovery, gain control, and, in some applications, for limiting path memory requirements of Viterbi detectors. For example, conventional peak detection systems typically employ run length limited (RLL) (d,k) constrained codes. These codes are normally found in optical recording systems and in relatively low linear-density magnetic recording systems. At moderate linear densities, the introduction of Partial Response Maximum Likelihood (PRML) detection to hard disk drive data storage devices involved the use of a different class of constrained codes known as (G,I) codes. As demonstrated by J. Moon and B. Brickner, xe2x80x9cMaximum transition run codes for data storage systems,xe2x80x9d IEEE Trans. Magn., vol. 32, pp. 3992-3994, September 1996 and R. D. Cideciyan, E. Eleftheriou, B. Marcus, and D. Modha xe2x80x9cMaximum Transition Run Codes for Generalized Partial-Response Channelsxe2x80x9d IEEE J. Select. Areas Commun., 19(4), pp. 619-634, April 2001, maximum transition run (MTR) (j,k) codes have been introduced to provide run length limited properties and to enhance the detector performance. A 16/17 code combining an 8 bit unconstrained code with a nine bit (G,I) constrained byte is described in both J. Sonntag, xe2x80x9cApparatus and method for increasing density of run length limited block codes without increasing error propagation,xe2x80x9d U.S. Pat. No. 5,604,497 and Coker, above. A 1/(1+D2) precoder is also employed in Sonntag, above, and J. Coker, D. Flynn, R. Galbraith, T. Truax, xe2x80x9cMethod and apparatus for implementing a set rate code for data channels with alternate 9-bit code words and 8-bit code words,xe2x80x9d U.S. Pat. No. 5,784,010. High rate codes produced by interspersing MTR code words with uncoded source symbols are described in A. Wijngaarden, E. Soljanin, xe2x80x9cA combinatorial technique for constructing high-rate MTR-RLL codes,xe2x80x9d IEEE J. Select. Areas Commun., 19(4), pp. 582-588, April 2001. A 1(1+D) precoder is employed in A. Wijngaarden, above. All of the aforementioned codes are designed on the basis of a precoder being present at the output of the constrained code encoder. At the receiver side, the precoder operation is undone by an inverse precoder circuit. However, the inverse precoder causes error propagation that adversely affects the performance. For example, the inverse precoder can cause an increase in sector error rate of the outer Reed-Solomon (RS) code. In applications such as magnetic recording, the code rate is subject to a stringent requirement.
In accordance with the present invention, there is now provided a modulation encoder having a finite state machine for converting input bits into output bits in which the number of alternating output bits is limited to j+1 where j is a predefined maximum number of transitions in the output bits, and in which the number of like output bits is limited to k+1 where k is a predefined maximum number of non-transitions in the output bits.
Viewing the present invention from a different aspect, there is now provided, a modulation encoder having a finite state machine for converting input bits into output bits in which the number of like output bits is at least d+1 and at most k+1 where d is a predefined minimum number of non-transitions in the output bits and k is a predefined maximum number of non-transitions in the output bits.
In a preferred embodiment of the present invention, there is provided encoding apparatus for converting an input bit stream into an output bit stream, the apparatus comprising: partitioning logic for partitioning the input bit stream into a first group of bits and a second group of bits; at least one modulation encoder of one of the forms herein before described connected to the partitioning logic for converting the first group of bits into coded output bits; and, combining logic connected to the or each modulation encoder and the partitioning logic for combining the coded output bits and the second group of bits to generate the output bit stream. The encoding apparatus may comprise a plurality of modulation encoders as herein before described each for converting a different subgroup of the first group of bits into coded output bits, wherein the different subgroups of the first group of bits are interleaved with different subgroups of the second group of bits. The apparatus may additionally or alternatively comprise a parity generator connected to the or each modulation encoder and the partitioning logic for generating a parity code in dependence on the second group of bits and the coded output bits. The combining logic preferably comprises a parallel to serial convertor connected to the or each modulation encoder and the partitioning logic.
Viewing the present invention from another aspect, there is now provided a modulation decoder having a sliding block decoder logic for recovering output bits from input bits in which the number of alternating input bits is limited to j+1 where j is a predefined maximum number of transitions in the input bits, and in which the number of like input bits is limited to k+1 where k is a predefined maximum number of non-transitions in the input bits.
Viewing the present invention from yet another aspect, there is now provided a modulation decoder having sliding block decoder logic for recovering output bits from input bits in which the number of like input bits is at least d+1 and at most k+1 where d is a predefined minimum number of non-transitions in the input bits and k is a predefined maximum number of non-transitions in the input bits.
In another preferred embodiment of the present invention, there is provided decoding apparatus for decoding an input bit stream into an output bit stream, the apparatus comprising: partitioning logic for partitioning the input stream into a first group of bits and a second group of bits; at least one modulation decoder of one of the forms herein before described connected to the partitioning logic for decoding the first group of bits into decoded output bits; and, combining logic connected to the or each modulation decoder and the partitioning logic for combining the second group of bits and the decoded output bits. Such apparatus may comprise a plurality of modulation decoders as herein before described each for converting a different subgroup of the first group of bits into decoded output bits, wherein the different subgroups of the first group of bits are interleaved with different subgroups of the second group of bits. The partitioning logic of the decoding apparatus may comprise a serial to parallel convertor connected to the or each modulation decoder.
It will be appreciated that the present invention extends to a signal processing device comprising encoding apparatus and decoding apparatus as herein before described. Similarly, it will be appreciated that the present invention extends to a data storage device comprising a data storage channel, together with encoding apparatus and encoding apparatus as herein before described.
Viewing the present invention from yet another aspect, there is provided a bit encoding method comprising, via a finite state machine, converting input bits into output bits in which the number of alternating output bits is limited to j+1 where j is a predefined maximum number of transitions in the output bits, and in which the number of like output bits is limited to k+1 where k is a predefined maximum number of non-transitions in the output bits.
In accordance with the present invention, there is also provided a bit encoding method comprising, via a finite state machine, converting input bits into output bits in which the number of like output bits is at least d+1 and at most k+1 where d is a predefined minimum number of non-transitions in the output bits and k is a predefined maximum number of non-transitions in the output bits.
In yet another preferred embodiment of the present invention, there is provided a data encoding method for converting an input bit stream into an output bit stream, the method comprising: partitioning the input bit stream into a first group of bits and a second group of bits; converting the first group of bits into coded output bits according to one of the bit encoding methods herein before described; and, combining the coded output bits and the second group of bits to generate the output bit stream.
Viewing the present invention from a further aspect, there is now provided a bit decoding method comprising, via sliding block decoder logic, recovering output bits from input bits in which the number of alternating input bits is limited to j+1 where j is a predefined maximum number of transitions in the input bits, and in which the number of like input bits is limited to k+1 where k is a predefined maximum number of non-transitions in the input bits.
In accordance with the present invention, there is further provided a bit decoding method comprising, via sliding block decoder logic, recovering output bits from input bits in which the number of like input bits is at least d+1 and at most k+1 where d is a predefined minimum number of non-transitions in the input bits and k is a predefined maximum number of non-transitions in the input bits.
In a further preferred embodiment of the present invention, there is now provided a data decoding method for decoding an input bit stream into an output bit stream, the method comprising: partitioning logic for partitioning the input bit stream into a first group of bits and a second group of bits; decoding the first group of bits into decoded output bits via one of the bit decoding methods herein before described; and, combining the second group of bits and the decoded output bits.
In a preferred embodiment of the present invention to be described in detail shortly, byte-oriented (m-bit bytes) precoderless constrained codes are provided. In a particularly preferred embodiment of the present invention, these codes are conveniently combined with multiparity block codes to provide a further enhancement of system performance. In an especially preferred embodiment of the present invention, a very high rate precoderless inner code is provided by concatenating unconstrained bits with constrained n-bit bytes. The constrained n-bit bytes are obtained by encoding unconstrained m-bit bytes (n greater than m). In applications using outer RS codes, the m-bit bytes can be matched to the symbol size of the RS code to minimize error propagation. Preferred embodiments of the present invention include: apparatus and methods for providing rate 96/102 codes with two 8/9 (G,I) constrained bytes and four parity bits; apparatus and methods for providing rate 96/100 codes with two 8/9 MTR (j=1,2,3)) constrained bytes and 2 parity bits; apparatus and methods for providing rate 96/102 codes with three 8/9 MTR (j=1,2,3)) constrained bytes and 3 parity bits; and, apparatus and methods for providing rate 96/102 codes with two 8/9 MTR (j=2,3)) constrained bytes and 4 parity bits.